rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADM690A/adm692a/adm802l/m/adm805l/m one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1996 microprocessor supervisory circuits functional block diagram battery switchover reset generator watchdog transition detector (1.6s) 4.65v* 1.25v *4.4v for adm692a/adm802m/adm805m ADM690A adm692a adm802l adm802m adm805l adm805m power fail output (pfo) reset v out v batt v cc watchdog input (wdi) power fail input (pfi) (reset) ( ) = adm805l/m only features precision supply voltage monitor 4.65 v ADM690A/adm802l/adm805l 4.40 v adm692a/adm802m/adm805m reset assertion down to 1 v v cc reset timeout200 ms watchdog timer1.6 s 100 m a quiescent supply current automatic battery backup power switching voltage monitor for power fail 6 2% power fail accuracy on adm802l/m space-saving microsoic package (ADM690A) applications microprocessor systems computers controllers intelligent instruments general description the ADM690A/adm692a/adm802l/m/adm805l/m family of supervisory circuits offers complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. these functions include m p reset, backup battery switchover, watchdog timer, and power failure warning. the ADM690A/adm692a/adm802l/m/adm805l/m are available in 8-pin packages and provide: 1. power-on reset output during power-up, power-down and brownout conditions. the reset output remains opera- tional with v cc as low as 1 v. 2. battery backup switching for cmos ram, cmos microprocessor or other low power devices. 3. a reset pulse if the optional watchdog timer has not been toggled within 1.6 seconds. 4. a 1.25 v threshold detector for power fail warning, low bat tery detection, or to monitor a power supply other than +5 v. on the ADM690A/adm802l/adm805l the reset voltage threshold is 4.65 v. on the adm692a/adm802m/ adm805m, the reset voltage threshold is 4.40 v. the adm802l/adm802m guarantee power fail accuracies to 2%. the adm805l/m provides an active high reset output, reset instead of reset. the family of products is fabricated using an advanced epitaxial cmos process combining low power consumption and high reliabili ty. reset assertion is guaranteed with v cc as low as 1 v. they provide a pin-compatible upgrade for the max690a/ max692a/max802l/max802m/max805l all parts are available in 8-pin dip and soic packages. the ADM690A is also available in a new space-saving microsoic package.
ADM690A/adm692a/adm802l/m/adm805l/mCspecifications C2C rev. 0 (v cc = 4.75 v to 5.5 v (ADM690A/adm802l/adm805l), v cc = 4.5 v to 5.5 v, (adm692a/adm802m/adm805m), v batt = +2.8 v, t a = t min to t max unless otherwise noted) parameter min typ max units test conditions/comments v cc /v batt operation 1 v cc operating voltage range 1.0 5.5 v supply current (excludes i out ) 70 100 m a supply current in battery backup mode 0.05 1.0 m av cc = 0 v, v batt = 2.8 v battery standby current 5.5 v > v cc > v batt + 0.2 v (+ = discharge, C = charge) C0.1 +0.02 m a v out output voltage v cc C 0.02 v cc C 0.01 v i out = 5 ma v cc C 0.5 v cc C 0.05 v i out = 50 ma v cc C 0.02 v i out = 250 ma v out in battery backup mode v batt C 0.05 v batt C 0.002 v i out = 250 m a, v cc < v batt C 0.2 v battery switchover threshold 20 mv power up C20 mv power down battery switchover hysteresis 40 mv reset threshold reset voltage threshold ADM690A, adm802l, adm805l 4.5 4.65 4.75 v adm692a, adm802m, adm805m 4.25 4.4 4.5 v adm802l 4.55 4.7 v t a = 25 c, v cc falling adm802m 4.30 4.45 v t a = 25 c, v cc falling reset threshold hysteresis 40 mv reset timeout delay 140 200 280 ms reset output voltage v cc C 1.5 v i source = 800 m a 0.4 v i sink = 3.2 ma 0.3 v i sink = 100 m a, v cc = 1 v reset output voltage 0.8 v i source = 4 m a, v cc = 1.1 v v cc C 1.5 v adm805l/m, i source = 800 m a 0.4 v adm805l/m, i sink = 3.2 ma watchdog timer watchdog timeout period 1.0 1.6 2.25 s wdi input pulse width 50 ns v il = 0.4, v ih = 0.8 (v cc ) wdi input threshold logic low 0.8 v logic high 3.5 v wdi input current 10 m a wdi = v cc C10 m a wdi = 0 v power fail detector pfi input threshold 1.20 1.25 1.30 v ADM690A, adm692a, adm805l/m 1.225 1.25 1.275 v adm802l/m pfi input current C25 0.01 +25 na pfo output voltage v cc C 1.5 v i source = 800 m a 0.4 v i sink = 3.2 ma notes 1 either v cc or v batt can be 0 v if the other > +2.0 v. specifications subject to change without notice.
ADM690A/adm692a/adm802l/m/adm805l/m C3C rev. 0 absolute maximum ratings* (t a = +25 c unless otherwise noted) v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v v batt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v all other inputs . . . . . . . . . . . . . . . . . . C0.3 v to v cc + 0.3 v input current v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 ma v batt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma digital output current . . . . . . . . . . . . . . . . . . . . . . . . 20 ma power dissipation, n-8 dip . . . . . . . . . . . . . . . . . . . 400 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 120 c/w power dissipation, so-8 soic . . . . . . . . . . . . . . . . . 500 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . 110 c/w operating temperature range industrial (a version) . . . . . . . . . . . . . . . . C40 c to +85 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c storage temperature range . . . . . . . . . . . . C65 c to +150 c esd rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4 kv *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods of time may affect device reliability. ordering guide temperature package model range option ADM690Aan C40 c to +85 c n-8 ADM690Aarn C40 c to +85 c so-8 ADM690Aarm C40 c to +85 c rm-8 adm692aan C40 c to +85 c n-8 adm692aarn C40 c to +85 c so-8 adm802lan C40 c to +85 c n-8 adm802larn C40 c to +85 c so-8 adm802man C40 c to +85 c n-8 adm802marn C40 c to +85 c so-8 adm805lan C40 c to +85 c n-8 adm805larn C40 c to +85 c so-8 adm805man C40 c to +85 c n-8 adm805marn C40 c to +85 c so-8 pin configurations pin function description mnemonic function v cc power supply input: +5 v nominal. v batt backup battery input. as v cc falls below the reset threshold and below v batt by 20 mv, v batt will be switched to v out . on power-up as v cc rises to 20 mv above v batt , v out will be switched back to v cc . v out output voltage. when v cc is above the reset threshold, v out is connected to v cc through an on chip switch. when v cc is below the reset threshold, the higher of v cc or v batt is connected to v out . gnd 0 v. ground reference for all signals. pfi power fail comparator input. if pfi is less than 1.25 v, the power fail output pfo goes low. if unused, pfi should be connected to v cc or gnd. pfo power fail comparator output. if pfi is less than 1.25 v, the power fail output pfo goes low. reset logic output. reset goes low if 1. v cc falls below the reset threshold 2. the watchdog timer is not serviced within its timeout period (1.6 seconds) the reset threshold is typically 4.65 v for the ADM690A/adm802l/adm805l and 4.4 v for the adm692a/ adm802m/adm805m. reset remains low for 200 ms after v cc returns above the threshold. reset also goes low for 200 ms if the watchdog timer is enabled but not serviced within its timeout period. reset active high reset output (adm805l/m only). this is the inverse of reset . the asserted (high) level is v cc or v batt whichever is higher. wdi watchdog input. wdi is a three level input. if wdi remains either high or low for longer than 1.6 s, (reset) (reset) is activated. the timer resets with each transition on the wdi line. the watchdog timer may be disabled if wdi is left floating or is connected to a high impedance three stated logic output. 1 2 3 4 8 7 6 5 top view (not to scale) ADM690A adm692a adm802l adm802m adm805l adm805m pfo wdi reset (reset) v batt v out v cc gnd pfi
ADM690A/adm692a/adm802l/m/adm805l/m C4C rev. 0 typical performance curves i out ?ma v out ?v 3 2.75 2 10 70 20 30 40 50 60 2.5 2.25 r out = 9.3 w figure 1. output voltage vs. load current in battery backup 10 0% 100 90 2? 200mv pfo 1.3v pfi 1.2v figure 2. power fail comparator response time l y h 10 0% 100 90 10? 1v 5v v cc reset 4v t a = +25 8 c figure 3. ADM690A reset response time i out ?ma v out ?v 5.00 4.92 4.84 20 200 50 100 150 4.9 4.88 4.86 4.98 4.96 4.88 r out = 0.53 w figure 4. output voltage vs. load current in normal operation 10 0% 100 90 2? 200mv t a = +25 8 c 5v pfo 1.3v pfi 0v 1.2v figure 5. power fail comparator response time h y l 10 0% 100 90 400ms 1v figure 6. reset output voltage vs. v cc
ADM690A/adm692a/adm802l/m/adm805l/m C5C rev. 0 battery switchover reset generator watchdog transition detector (1.6s) 4.65v* 1.25v *4.4v for adm692a/adm802m/adm805m ADM690A adm692a adm802l adm802m adm805l adm805m power fail output (pfo) reset v out v batt v cc watchdog input (wdi) power fail input (pfi) (reset) ( ) = adm805l/m only figure 7. functional block diagram power fail reset , reset reset is an active low output which provides a reset signal to the microprocessor whenever v cc is at an invalid level. when v cc falls below the reset threshold, the reset output is forced low. the nominal reset voltage threshold is 4.65 v (ADM690A/ adm802l/adm805l or 4.4 v adm692a/adm802m/ adm805m. on power-up reset will remain low for 200 ms after v cc rises above the reset threshold. this allows time for the power supply and microprocessor to stabilize. on power-down, the reset output remains low with v cc as low as 1 v. this ensures that the microprocessor is held in a stable shutdown condition. the guaranteed minimum and maximum thresholds are as follows: ADM690A/adm802l/adm805l: 4.5 v and 4.75 v adm692a: 4.25 v and 4.5 v. adm802l: 4.55 v and 4.7 v adm802m: 4.3 v and 4.45 v the adm805l and adm805m contain an active high reset output. this is the complement of reset and is intended for processors requiring an active high reset signal. the guaranteed minimum and maximum thresholds for the adm805 are: adm805l: 4.5 v and 4.75 v adm805m: 4.25 v and 4.5 v. watchdog timer reset , reset the watchdog timer circuit monitors the activity of the micro- processor in order to check that it is not stalled in an indefinite loop. an output line on the processor is used to toggle the watchdog input (wdi) line. if this line is not toggled within 1.6 seconds, a reset pulse is generated. the watchdog timeout period restarts with each transition on the wdi pin. to ensure that the watchdog timer does not time out, either a high-to-low or low-to-high transition on the wdi pin must occur at or less than the minimum timeout period. if wdi remains permanently either high or low, reset pulses will be issued after each timeout period (1.6 s). the watchdog monitor can be deactivated by floating the watchdog input (wdi) or by connecting it to midsupply. +5v 0v +5v 0v +5v 0v +5v 0v 0v 3.0v 3.0v t rs v cc v out reset reset pfo v batt = pfi = 3.0v figure 8. timing diagram battery switchover section during normal operation with v cc higher than the reset threshold, v cc is internally switched to v out via an internal pmos transistor switch. this switch has a typical on-resistance of less than 1 w and can supply up to 100 ma at the v out terminal. once v cc falls below the reset threshold, the higher of v cc or v batt is switc hed to v out . this means that v batt connects to v out only when v cc is below the reset threshold and v batt is greater than v cc . v out is normally used to drive a ram memory bank which may require instantaneous currents of greater than 100 ma. if this is the case, then a bypass capacitor should be connected to v out . the capacitor will provide the peak current transients to the ram. a capacitance value of 0.1 m f or greater may be used. a 9 w mosfet switch connects the v batt input to v out during battery backup. this mosfet has very low input-to- output differential (dropout voltage) at the low current levels required for battery backup of cmos ram or other low power cmos circuitry. the supply current in battery backup is typically 0.05 m a. typically 3 v batteries are used as the backup supply. high value capacitors, either standard electrolytic or the farad size double layer capacitors, can also be used for short-term memory back up. a small charging current of typically 10 na (0.1 m a max) flows out of the v batt terminal. this current is useful for maintaining rechargeable batteries in a fully charged condition. this extends the life of the back up battery by compensating for its self discharge current. also note that this current poses no problem when lithium batteries are used for back up since the maximum charging current (0.1 m a) is safe for even the smallest lithium cells. if the battery-switchover section is not used, v batt should be connected to gnd and v out should be connected to v cc .
ADM690A/adm692a/adm802l/m/adm805l/m C6C rev. 0 table i. input and output status in battery backup mode signal status v out v out is connected to v batt via an internal pmos switch. reset logic low. reset logic high (adm805l, adm805m). the open circuit output voltage is equal to v out . pfi the power fail comparator is disabled pfo logic low. wdi the watchdog timer is disabled power fail comparator the power fail comparator is an independent comparator that may be used to monitor the input power supply. the comparators i nverting input is internally connected to a 1.25 v reference voltage. the noninverting input is available at the pfi input. this input may be used to monitor the input power supply via a resistive divider network. when the voltage on the pfi input drops below 1.25 v, the comparator output ( pfo ) goes low indicating a power failure. for early warning of power failure the comparator may be used to monitor the preregulator input simply by choosing an appropriate resistive divider network. the pfo output can be used to interrupt the processor so that a shutdown procedure is implemented before the power is lost. 1.25v power fail output (pfo) power fail input input power r1 r2 figure 9. power fail comparator adding hysteresis to the power fail comparator for increased noise immunity, hysteresis may be added to the power fail comparator. since the comparator circuit is non- inverting, hysteresis can be added simply by connecting a resistor between the pfo output and the pfi input as shown in figure 10. when pfo is low, resistor r3 sinks current from the summing junction at the pfi pin. when pfo is high, resistor r3 sources current into the pfi summing junction. this results in differing trip levels for the comparator. further noise immunity may be achieved by connecting a capacitor between pfi and gnd. 1.25v (pfo) input power r1 r2 pfi r3 to ? nmi 5v pfo 0v 0v v l v h v in v h = 1.25 1 + r 1 r 2 +r 3 r 2 r 3 v l = 1 .25 +r 1 1.25 v cc 1.25 r 2 r 3 v mid = 1.25 r 1 +r 2 r 2 figure 10. adding hysteresis to the power fail comparator typical applications figure 11 shows a typical power monitoring, battery backup application. v out powers the cmos ram. under normal operating conditions with v cc present, v out is internally connected to v cc . if a power failure occurs, v cc will decay and v out will be switched to v batt thereby maintaining power for the cmos ram. a reset pulse is also generated when v cc falls below the reset threshold. cmos ram power ? reset ? nmi i/o line ? system v cc ? power v out reset pfo wdi gnd v batt pfi unregulated dc r1 r2 +5v battery + figure 11. typical application circuit the watchdog timer input (wdi) monitors an i/o line from the m p system. this line must be toggled once every 1.6 seconds to verify correct software execution. failure to toggle the line indicates that the m p system is not correctly executing its program and may be tied up in an endless loop. if this happens, a reset pulse is generated to initialize the processor.
ADM690A/adm692a/adm802l/m/adm805l/m C7C rev. 0 if the watchdog timer is not needed, the wdi input should be left floating. the power fail input, pfi, monitors the input power supply via a resistive divider network. the voltage on the pfi input is compared with a precision 1.25 v internal reference. if the input voltage drops below 1.25 v, a power fail output ( pfo ) signal is generated. this warns of an impending power failure and may be used to interrupt the processor so that the system may be shut down in an orderly fashion. the resistors in the sensing network are ratioed to give the desired power fail threshold voltage v t . v t = (1.25 r 1/ r 2) + 1.25 v r 1/ r 2 = ( v t /1.25) C 1 alternate watchdog input drive circuits the watchdog feature can be enabled and disabled under program control by driving wdi with a 3-state buffer. when three-stated, the wdi input will float thereby disabling the watchdog timer. high capacity backup capacitors high capacity (0.1 m f or greater) capacitors may be used as a backup po wer source. a typical application is shown in fig- ure 12. v cc v out reset reset * gnd v batt +5v + 0.1f to static ram to ? * for adm805l/adm805m only figure 12. high capacity capacitor operation without a backup supply if a backup power source is not used, v batt should be con- nected to gnd and v out should be connected to v cc . replacing the backup battery the backup battery may be replaced without any danger of spurious resetting when v cc is present. since v cc is above the reset threshold, a reset will not occur even if v batt is floating while a replacement battery is being inserted. this differs from older generation products where leakage currents flowing out v batt could cause spurious resetting during battery replacement. m ps with bidirectional reset in order to prevent contention for microprocessors with a bidirectional reset line, a current limiting resistor should be inserted between the adm69xa/adm80xx reset output pin and the m p reset pin. this will limit the current to a safe level if there are conflicting output reset levels. a suitable res istor value is 4.7 k w . if the reset output is required for other uses, then it should be buffered as shown in figure 13. reset ? v cc gnd +5v reset gnd ADM690A adm692a adm802l adm802m buffered reset figure 13. bidirectional reset
ADM690A/adm692a/adm802l/m/adm805l/m C8C rev. 0 outline dimensions dimensions shown in inches and (mm). c2197C12C10/96 printed in u.s.a. 8-pin plastic dip (n-8) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.130 (3.30) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 8-lead soic (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 8-lead microsoic (rm-8) 8 5 4 1 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) seating plane 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) 0.008 (0.20) 0.043 (1.09) 0.037 (0.938) 0.120 (3.05) 0.112 (2.84) 0.011 (0.28) 0.003 (0.08) 0.027 (0.68) 0.015 (0.38) 33 27 0.120 (3.05) 0.112 (2.84)
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